RTL Design Engineer

Google is seeking an RTL Design Engineer to join their team developing custom silicon solutions for direct-to-consumer products. This role focuses on designing interconnect IP for Pixel System on Chip (SoCs), requiring expertise in hardware design, microarchitecture, and RTL development.

The position involves collaborating with cross-functional teams including architecture, software, verification, power, and timing to deliver high-quality Register-Transfer Level (RTL) designs. The successful candidate will solve technical challenges related to micro-architecture, RTL, and low power design methodology, while evaluating design options for optimal performance, power, and area.

This is an opportunity to work on cutting-edge hardware that powers Google's consumer products, contributing to innovations that impact millions of users worldwide. The role combines hardware expertise with Google's strengths in AI and software to create next-generation computing experiences.

Key responsibilities include developing microarchitecture specifications, implementing RTL designs in SystemVerilog, performing quality checks, and working on synthesis and timing/power estimation. The position requires strong technical skills in hardware design and excellent collaboration abilities to work effectively with multi-disciplined, multi-site teams.

The ideal candidate will have experience with ARM-based SoCs, ARM-protocols, and ASIC methodology, along with programming skills in languages like Perl or Python. This role offers the chance to shape the future of Google's hardware experiences while working with state-of-the-art technology and talented teams.