RTL Design Engineer, University Graduate, PhD, Machine Learning
Description For RTL Design Engineer, University Graduate, PhD, Machine Learning
Google is seeking a PhD-level RTL Design Engineer to join their ML, Systems, & Cloud AI (MSCA) organization. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products, with a specific emphasis on clock control subsystems and ASIC development.
The position offers an opportunity to work on cutting-edge hardware that supports Google's vast service infrastructure, including Search, YouTube, and Google Cloud. You'll be part of a team that designs and implements hardware solutions for hyperscale computing, with particular focus on TPUs and machine learning acceleration.
The role requires expertise in RTL coding, SystemVerilog, and digital clock control circuits. You'll work independently on microarchitecture specifications while collaborating with cross-functional teams in architecture, power, design validation, and physical design. The position demands both technical depth in hardware design and the ability to work effectively across teams.
This is an excellent opportunity for someone with a PhD in Electrical Engineering, Computer Engineering, or Computer Science who wants to impact billions of users through hardware innovation. The role offers competitive compensation ($132,000-$189,000 base salary plus bonus, equity, and benefits) and the chance to work at Google's offices in either Madison, WI or Sunnyvale, CA.
Key responsibilities include developing SystemVerilog RTL, creating microarchitecture specifications, and ensuring designs meet quality guidelines and physical requirements. The ideal candidate will have experience with processor design or accelerators, knowledge of high-performance and low power design techniques, and familiarity with scripting languages like Python.
Google offers a comprehensive benefits package and maintains a strong commitment to diversity, equity, and inclusion. The company actively seeks to build a workforce representative of its global user base and fosters a culture of belonging for all employees.
Responsibilities For RTL Design Engineer, University Graduate, PhD, Machine Learning
- Work mostly independently to create and review clock control subsystem's design microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work with architecture and power teams to evaluate features and their impact
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For RTL Design Engineer, University Graduate, PhD, Machine Learning
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog
Benefits For RTL Design Engineer, University Graduate, PhD, Machine Learning
- Medical Insurance
- Equity
- 401k
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