Senior ASIC Design Engineer, Silicon

Join Google's Silicon team as a Senior ASIC Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. As part of the team designing foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and peripherals) for Pixel SoCs, you'll collaborate across multiple disciplines including architecture, software, verification, power, and timing.

Your role involves solving complex technical challenges through innovative micro-architecture and low power design methodology, while carefully balancing complexity, performance, power, and area considerations. You'll be working on RTL development using SystemVerilog, performing quality checks, and participating in various stages of the design process from synthesis to silicon bring-up.

Google's mission centers on organizing world's information and making it universally accessible. The team combines Google's expertise in AI, Software, and Hardware to create groundbreaking helpful experiences. Working here means contributing to technologies that make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.

The position requires strong technical expertise in ASIC design, with preferred experience in low power estimation, timing closure, and synthesis methodologies. You'll be working with state-of-the-art tools and methodologies for RTL quality checks, and should be comfortable with scripting languages like Python or Perl. This is an opportunity to shape the future of Google's hardware experiences, delivering unparalleled performance, efficiency, and integration in products used by millions worldwide.