Senior ASIC Design Performance Verification Engineer, Silicon
Description For Senior ASIC Design Performance Verification Engineer, Silicon
Join Google's innovative hardware team as a Senior ASIC Design Performance Verification Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google's AI, Software, and Hardware capabilities to create groundbreaking experiences used by millions worldwide.
As a performance verification engineer, you'll be responsible for ensuring the quality and efficiency of next-generation configurable infrastructure IPs, interconnects, and memory subsystems. Your work will involve developing comprehensive test plans, analyzing performance data, and working closely with architecture and design teams to achieve optimal results.
The position requires expertise in SystemVerilog and UVM, with a focus on simulating digital reasoning at the Register-Transfer Level (RTL). You'll be working with advanced technologies including Cache Hierarchies, Memory Consistency Models, and various interconnect protocols such as AHB, AXI, and CXL.
At Google, you'll be part of a team that pushes boundaries and shapes the future of hardware experiences. The company's mission to organize the world's information and make it universally accessible drives the development of radically helpful experiences through the combination of AI, software, and hardware innovation.
This role offers the opportunity to work on cutting-edge technology while contributing to products that impact users globally. You'll be part of Google's commitment to delivering unparalleled performance, efficiency, and integration in their hardware solutions, making computing faster, seamless, and more powerful.
Responsibilities For Senior ASIC Design Performance Verification Engineer, Silicon
- Develop a performance verification test plan from architecture specifications and goals
- Analyze performance data and conduct reviews with architecture and design teams
- Plan and execute the performance verification of the next generation configurable infrastructure IPs, interconnects and memory subsystems
- Use constrained-random verification environments and develop stimulus
- Enhance existing performance monitors and scoreboard infrastructure using SystemVerilog and UVM
- Verify the impact of low power optimization on performance
Requirements For Senior ASIC Design Performance Verification Engineer, Silicon
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience
- 5 years of experience in simulating digital reasoning at Register-Transfer Level (RTL) using SystemVerilog and UVM
- 5 years of experience in performance verification for IPs
- Experience in Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL)
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