Senior ASIC Design Verification Engineer, TPU Compute

Join Google's ML, Systems, & Cloud AI (MSCA) organization as a Senior ASIC Design Verification Engineer working on TPU (Tensor Processing Unit) technology. In this role, you'll be at the forefront of AI/ML hardware acceleration, verifying complex digital designs for Google's custom silicon solutions that power their most demanding AI/ML applications. The position offers the opportunity to work on cutting-edge technology that impacts billions of users worldwide through Google's services and Cloud platform.

The role involves working with state-of-the-art verification methodologies using SystemVerilog and UVM, collaborating closely with design engineers to ensure the functional correctness of TPU architecture components. You'll be responsible for creating comprehensive verification environments, developing coverage metrics, and driving verification closure for critical hardware designs.

This is an excellent opportunity for experienced verification engineers who want to make a significant impact on the future of AI hardware acceleration. You'll be part of a team that prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. The position offers competitive compensation including base salary, bonus, equity, and comprehensive benefits, reflecting Google's commitment to attracting top talent in the field.

The role requires deep expertise in digital design verification, particularly in memory subsystems and ASIC interfaces. You'll work in Sunnyvale, CA, contributing to Google's mission of advancing AI/ML capabilities through hardware innovation. The position offers growth opportunities within Google's dynamic engineering environment and the chance to work on technology that shapes the future of cloud computing and AI acceleration.