Senior CPU Design Verification Engineer
Description For Senior CPU Design Verification Engineer
Google's ML, Systems & Cloud AI (MSCA) organization is seeking a Senior CPU Design Verification Engineer to join their server chip design team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. You'll work within an R&D team, focusing on building verification components, constrained-random testing, system testing, and verification closure.
The position involves collaborating closely with design and verification engineers, managing the full lifecycle of verification from planning to coverage closure. You'll be responsible for creating efficient verification environments that thoroughly test designs through their corner-cases to identify potential issues. The role requires expertise in SystemVerilog/UVM or Specman, along with strong debugging and analytical skills.
As part of MSCA, you'll contribute to the infrastructure supporting all Google services (Search, YouTube, etc.) and Google Cloud. The organization prioritizes security, efficiency, and reliability, working on cutting-edge technologies including TPUs and hyperscale computing. Your work will directly impact Google Cloud's Vertex AI, the leading AI platform for enterprise customers using Gemini models.
This is an excellent opportunity for experienced verification engineers who want to shape the future of hardware experiences at Google, delivering unparalleled performance, efficiency, and integration. The role offers the chance to work on products used by billions of people worldwide, making a significant impact on Google's hardware infrastructure.
Responsibilities For Senior CPU Design Verification Engineer
- Plan the verification of digital design blocks by understanding design specification and identifying important verification scenarios
- Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Lead coverage measures to identify verification holes and show progress towards tape-out
Requirements For Senior CPU Design Verification Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 8 years of experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs
- Experience verifying digital systems using standard IP components/interconnects
- Experience creating and using verification components and environments in standard verification methodology
- Experience with CPU implementation, assembly language, or compute System on a Chip (SOC)
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