Silicon Design Verification Engineer, Silicon

Google organizes the world's information and makes it universally accessible and useful through innovative technology products.
$132,000 - $189,000
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
AI · Consumer

Description For Silicon Design Verification Engineer, Silicon

Join Google's Devices & Services team as a Silicon Design Verification Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google AI, Software, and Hardware to create innovative experiences for millions of users worldwide.

As a Silicon Design Verification Engineer, you'll be responsible for ensuring the functionality and reliability of digital design blocks through comprehensive verification processes. You'll work with SystemVerilog and Universal Verification Methodology (UVM) to create and enhance verification environments, collaborate closely with design engineers, and contribute to the development of next-generation hardware experiences.

The position offers competitive compensation including a base salary range of $132,000-$189,000, plus bonus, equity, and comprehensive benefits. You'll be part of Google's mission to organize the world's information and make it universally accessible and useful, while working on cutting-edge hardware solutions that push the boundaries of technology.

The role requires strong technical expertise in verification methodologies, excellent debugging skills, and the ability to collaborate effectively with cross-functional teams. You'll be involved in all aspects of the verification process, from planning and implementation to coverage analysis and tape-out preparation. This is an excellent opportunity for someone passionate about hardware verification and interested in working on products that impact millions of users.

Last updated 4 hours ago

Responsibilities For Silicon Design Verification Engineer, Silicon

  • Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers
  • Create and enhance constrained random verification environments using SystemVerilog and Universal Verification Methodology (UVM)
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Close coverage measures to identify verification holes and show progress towards tape out
  • Collaborate with architecture, design teams, Sival teams in defining the overall verification of the SoCs

Requirements For Silicon Design Verification Engineer, Silicon

Linux
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog
  • Experience in developing and maintaining verification testbenches, test cases, and test environments

Benefits For Silicon Design Verification Engineer, Silicon

Medical Insurance
401k
Equity
  • Bonus
  • Equity
  • Benefits package

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