Silicon Design Verification Engineer, TPU, Google Cloud
Description For Silicon Design Verification Engineer, TPU, Google Cloud
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a Silicon Design Verification Engineer working on TPU (Tensor Processing Unit) technology. In this role, you'll be at the forefront of AI/ML hardware acceleration, verifying complex digital designs that power Google's most demanding AI/ML applications. You'll own the full verification lifecycle, from planning to coverage closure, focusing on meeting stringent AI/ML performance and accuracy goals.
The position involves building constrained-random verification environments, collaborating with design engineers, and ensuring the reliability of AI/ML workloads on TPU hardware. You'll be part of a diverse team developing custom silicon solutions that power Google's future TPU technology, contributing to products used by millions worldwide.
Working in the MSCA organization, you'll be part of the team that designs, implements, and manages hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. The role emphasizes security, efficiency, and reliability while driving towards shaping the future of hyperscale computing. Your work will have global impact, including supporting Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
This is an excellent opportunity for someone with strong verification methodology experience and a passion for AI/ML hardware acceleration to make a significant impact on Google's next-generation TPU technology.
Responsibilities For Silicon Design Verification Engineer, TPU, Google Cloud
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Measure to identify verification holes and to show progress towards tape-out
- Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM)
Requirements For Silicon Design Verification Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 4 years of experience with verification methodology such as Universal verification methodology (UVM)
- 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
- Experience with SystemVerilog, SVA, and functional coverage
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