Silicon Networking RTL Design Engineer, Google Cloud
Description For Silicon Networking RTL Design Engineer, Google Cloud
Join Google Cloud as a Silicon Networking RTL Design Engineer, where you'll be at the forefront of AI/ML hardware acceleration technology. This role focuses on developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of the ML, Systems, & Cloud AI (MSCA) organization, working on custom silicon solutions that accelerate and improve traffic efficiency in data centers.
As a senior technical member, you'll collaborate with cross-functional teams in architecture, verification, power and performance, and physical design to deliver high-quality designs for next-generation data center accelerators. Your responsibilities will include solving complex technical problems through innovative micro-architecture and practical logic solutions, while considering factors like complexity, performance, power, and area optimization.
The position offers the opportunity to work on technology that impacts billions of users worldwide through Google's services and Google Cloud. You'll be contributing to the development of ASICs that are crucial for Google's infrastructure, working with state-of-the-art tools and methodologies in hardware design. The role combines deep technical expertise in hardware design with the excitement of working on next-generation AI acceleration technology.
This is an excellent opportunity for experienced hardware engineers who want to make a significant impact on Google's infrastructure while working with cutting-edge technology in AI/ML hardware acceleration. You'll be part of a diverse team that pushes boundaries and develops solutions that power the future of Google's TPU technology.
Responsibilities For Silicon Networking RTL Design Engineer, Google Cloud
- Own microarchitecture and implementation of complex IPs and subsystems in the Networking domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and lead power, performance, and area improvements for the domains owned
Requirements For Silicon Networking RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control, etc.
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