Silicon Subsystems RTL Design Engineer, Google Cloud

Google is seeking a Silicon Subsystems RTL Design Engineer to join their Google Cloud team, focusing on shaping the future of AI/ML hardware acceleration. This role is integral to the development of cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. The position is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for designing, implementing, and managing hardware, software, and infrastructure for all Google services and Google Cloud.

The role involves working on ASICs used to accelerate and improve data center traffic, collaborating with various teams including architecture, verification, power and performance, and physical design. You'll be responsible for developing custom silicon solutions that power Google's TPU, contributing to innovation behind products used by millions worldwide. The position requires expertise in design and verification of complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As part of the team, you'll solve technical problems through innovative micro-architecture and practical logic solutions, evaluating design options while considering complexity, performance, power, and area. The role offers an opportunity to work on projects that directly impact Google's global infrastructure and services, including Google Cloud's Vertex AI platform, which brings Gemini models to enterprise customers.

The ideal candidate should have strong experience in ASIC development, verification, and subsystem design, with knowledge of high-performance and low-power design techniques. This position offers the chance to work at the forefront of AI hardware development while contributing to Google's mission of organizing the world's information and making it universally accessible and useful.