SoC and IP Design Engineer, Google Cloud
Description For SoC and IP Design Engineer, Google Cloud
Join Google Cloud's innovative hardware team as a SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's next-generation cloud infrastructure. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on critical hardware components that support Google's vast service ecosystem, including Search, YouTube, and Google Cloud services. This role combines hardware expertise with cutting-edge technology, requiring strong skills in RTL design, SoC architecture, and low-power optimization.
You'll be responsible for designing and implementing complex System-on-Chip components, working with state-of-the-art tools and methodologies. The position offers the opportunity to work with advanced technologies like PCIe, UCIe, DDR, and ARM processors, while collaborating with multi-disciplinary teams across different locations. Your work will directly impact the performance and efficiency of Google's cloud infrastructure, serving billions of users worldwide.
This is an excellent opportunity for experienced hardware engineers who want to make a significant impact on large-scale computing systems. You'll be part of a team that prioritizes security, efficiency, and reliability, while pushing the boundaries of what's possible in hyperscale computing. The role offers exposure to cutting-edge AI infrastructure, including Google Cloud's Vertex AI platform, and the chance to work on projects that shape the future of cloud computing technology.
Working at Google means joining a company that values innovation, technical excellence, and collaborative problem-solving. You'll have access to world-class resources and the opportunity to work with some of the industry's brightest minds. The position offers competitive compensation and the chance to work on projects that have global impact.
Responsibilities For SoC and IP Design Engineer, Google Cloud
- Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
- Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
- Experience in reasoning design and debug with Design Verification (DV)
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