SoC and IP Design Engineer, Google Cloud
Description For SoC and IP Design Engineer, Google Cloud
Join Google Cloud's innovative hardware team as a SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's next-generation cloud infrastructure. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and machine learning infrastructure supporting all Google services and Cloud operations.
As a SoC and IP Design Engineer, you'll work on cutting-edge hardware designs, focusing on Register-Transfer Level (RTL) development, logic synthesis, and verification. You'll be involved in the entire development cycle, from defining block-level design documents to silicon bring-up. The position requires expertise in digital logic design, RTL concepts, and hardware description languages like Verilog or System Verilog.
The role offers the opportunity to work with state-of-the-art technology and contribute to projects that directly impact billions of users worldwide. You'll be part of a global team developing solutions for hyperscale computing, including advanced TPUs and network infrastructure. The position combines technical depth in hardware design with the breadth of Google's cloud computing platform.
Working at Google Cloud means joining a team that prioritizes security, efficiency, and reliability while pushing the boundaries of what's possible in cloud computing. You'll collaborate with experts across disciplines and locations, contributing to the innovation behind Google's hardware experiences and helping shape the future of cloud infrastructure.
Responsibilities For SoC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
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