SoC Physical Design Engineer, Implementation

Join Google's hardware team as a SoC Physical Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines technical expertise in physical design with the opportunity to impact products used by millions worldwide.

The position requires deep knowledge of ASIC design flows, physical design methodology, and experience with synthesis/PnR tools. You'll be responsible for implementing innovative methodology schemes to optimize Performance, Area, and Power, while managing physical implementation for partitions and developing RTL2GDS implementations.

Key technical areas include working with synthesis tools like Genus and Innovus, handling low power design implementation with UPF/CPF, and utilizing scripting languages such as TCL or Perl. Knowledge of computer architecture, Verilog/SystemVerilog, and understanding of circuit design and device physics are valuable assets.

The role offers competitive compensation ($132,000-$189,000 base salary) plus bonus, equity, and comprehensive benefits. You'll be working at Google's Mountain View location, collaborating with cross-functional teams to deliver cutting-edge silicon solutions.

This is an excellent opportunity for experienced physical design engineers looking to make a significant impact on Google's hardware products while working with state-of-the-art technology and tools. The role combines technical depth with the scale and resources of Google, offering both professional growth and the chance to influence the next generation of Google's hardware experiences.