SoC RTL Security Design Engineer
Description For SoC RTL Security Design Engineer
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a SoC RTL Security Design Engineer, where you'll be part of a team developing custom silicon solutions for Google's direct-to-consumer products. This role focuses on SoC-level RTL design for data center accelerators, with emphasis on security subsystems and management control. You'll be working on cutting-edge technology that powers Google's services and Cloud infrastructure, contributing to projects that impact billions of users worldwide.
The position requires expertise in RTL design, security implementation, and cross-functional collaboration. You'll be responsible for developing SystemVerilog RTL, creating microarchitecture specifications, and working closely with various teams including architecture, power, design validation, and physical design. The role offers competitive compensation including a base salary range of $132,000-$189,000, plus bonus, equity, and comprehensive benefits.
This is an excellent opportunity for someone with strong technical skills in hardware design and security, who wants to work on innovative projects at scale. You'll be part of Google's mission to shape the future of hyperscale computing, working on everything from TPUs to global network infrastructure. The role combines technical depth in hardware design with the broad impact of Google's technology stack.
The position is based in Sunnyvale, CA, and requires collaboration with multiple teams across Google's hardware and software divisions. You'll be working in an environment that prioritizes security, efficiency, and reliability, while contributing to products that are used by millions of people daily. This role offers significant growth potential and the chance to work with cutting-edge technology in a company known for innovation.
Responsibilities For SoC RTL Security Design Engineer
- Create and review the security subsystem's design microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work with architecture and power teams to evaluate security features and their impact
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For SoC RTL Security Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 3 years of experience with RTL coding using Verilog/SystemVerilog
- Experience with industry-standard EDA tools for simulation, synthesis and power analysis
Benefits For SoC RTL Security Design Engineer
- Bonus
- Equity
- Comprehensive benefits package
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