Static Timing Analysis Engineer, FullChip/ASIC Implementation
Description For Static Timing Analysis Engineer, FullChip/ASIC Implementation
Google is seeking a Static Timing Analysis Engineer to join their hardware team working on custom silicon solutions for direct-to-consumer products. This role focuses on delivering System-on-Chip (SoC) Static Timing Analysis and is crucial for developing the next generation of Google's hardware experiences. The position requires deep expertise in silicon timing closure, chip integration, and experience with static timing tools.
The ideal candidate will have at least 5 years of technical experience and will be responsible for defining SoC timing signoff processes, driving clock tree planning, and overseeing full chip timing constraint creation and validation. They will work on cutting-edge technology process nodes and contribute to innovations that power Google's products used by millions worldwide.
This is an excellent opportunity for someone with strong technical skills in ASIC design flows and methodology of static timing analysis. The role offers competitive compensation including base salary, bonus, equity, and comprehensive benefits. The position is based in either San Diego or Mountain View, California, working with Google's hardware teams to push the boundaries of custom silicon solutions.
The role combines technical expertise with strategic thinking, requiring both hands-on engineering skills and the ability to drive complex projects. It's an opportunity to work on challenging technical problems while contributing to products that have a significant impact on users worldwide. The position offers growth potential and the chance to work with cutting-edge technology in a collaborative environment.
Responsibilities For Static Timing Analysis Engineer, FullChip/ASIC Implementation
- Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis
- Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs
- Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area
- Oversee full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation, and final timing signoff for SoC's
Requirements For Static Timing Analysis Engineer, FullChip/ASIC Implementation
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of technical experience in silicon timing closure and chip integration
- Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation
- Experience in one or more static timing tools (e.g., PrimeTime, Tempus)
Benefits For Static Timing Analysis Engineer, FullChip/ASIC Implementation
- Bonus
- Equity
- Benefits package
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