RTL Design Engineer, University Graduate, PhD, Machine Learning
Description For RTL Design Engineer, University Graduate, PhD, Machine Learning
Google's ML, Systems, & Cloud AI (MSCA) organization is seeking an RTL Design Engineer to join their team developing custom silicon solutions for Google's direct-to-consumer products. This role is part of the team that designs and implements hardware infrastructure for all Google services and Google Cloud.
The position requires a PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field, with strong experience in RTL coding and Verilog/SystemVerilog. The ideal candidate will have expertise in digital clock control circuits, processor design, and high-performance computing.
As an RTL Design Engineer, you'll be responsible for creating microarchitecture specifications, developing SystemVerilog RTL for ASIC products, and collaborating with various teams including architecture, power, design validation, and physical design. The role offers an opportunity to work on cutting-edge technology that powers Google's services used by billions of people worldwide.
The position offers a competitive compensation package ranging from $132,000 to $189,000 base salary, plus bonus, equity, and comprehensive benefits. Located in either Madison, WI or Sunnyvale, CA, you'll be part of Google's innovative hardware team working on next-generation machine learning accelerators and systems.
This is an excellent opportunity for someone passionate about hardware design and machine learning, wanting to make a significant impact on Google's infrastructure and products. The role combines technical depth in digital design with the scale and complexity of Google's systems, making it an exciting challenge for experienced hardware engineers.
Responsibilities For RTL Design Engineer, University Graduate, PhD, Machine Learning
- Work mostly independently to create and review clock control subsystem's design microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work with architecture and power teams to evaluate features and their impact
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For RTL Design Engineer, University Graduate, PhD, Machine Learning
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog
- Experience with digital clock control circuits
- Experience with a scripting language (e.g., Python or Perl)
- Knowledge of processor design or accelerators
- Knowledge of high-performance and low power design techniques
Benefits For RTL Design Engineer, University Graduate, PhD, Machine Learning
- Medical Insurance
- Equity
- 401k
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