Staff Engineer, ASIC Digital Design
Description For Staff Engineer, ASIC Digital Design
GreenWave Radios™, formerly InnoPhase Inc., is a leading innovator in Open RAN digital radios. Based in San Diego, California, the company specializes in cutting-edge solutions powered by the Hermes64 RF SoC, designed to enhance network energy efficiency and reduce operational expenses. With over 100 talented engineers across four global R&D facilities and more than 120 patent filings, GreenWave Radios™ is committed to advancing radio technology.
As a Staff Engineer, ASIC Digital Design, you'll be part of a team developing novel 5G ORAN SoC products for connectivity and wireless communications. Your role will involve micro-architecture and design of digital functional blocks, contributing to high-quality digital solutions within the product architecture. You'll also support other disciplines with work products such as Verilog stimulus files, test benches, and test vectors for manufacturing.
Key responsibilities include:
- Designing and integrating SERDES controller, PCS, and PMA functional blocks
- Micro code development for network processors
- Network processor architecture, throughput analysis, and optimization
- Front-to-back ASIC digital design and verification
- Defining and reviewing synthesis constraints
- Debugging functional and timing closure issues
- Collaborating with System, Software, RF, Analog, and Test teams
The ideal candidate will have:
- MS/Ph.D. in EE/CS (preferred)
- 10+ years of experience in digital SoC development
- Strong knowledge of CPU bus protocols, Verilog/SystemVerilog RTL coding, and timing analysis
- Experience with embedded systems, wireless protocols, and standard digital interfaces
- Proficiency in languages such as C/C++, Perl, Tcl, and Python
This full-time position offers a competitive compensation package, including base pay between $130K-$190K, pre-IPO stock options, comprehensive health benefits, 401(k) matching, and various paid leaves. Join a company where 93% of current staff approve of the leadership, values, and goals, and contribute to the future of wireless communication technology.
Responsibilities For Staff Engineer, ASIC Digital Design
- Design and integrate SERDES controller, PCS, PMA functional blocks
- Micro code development for network processor
- Network processor architecture, throughput analysis and optimization
- Front-to-back ASIC digital design and verification – RTL through physical implementation
- Define & review synthesis constraints for functional blocks
- Functional issues debugging and timing closure issues debugging
- Work with System, Software, RF, Analog, and Test teams and provide the necessary support
Requirements For Staff Engineer, ASIC Digital Design
- MS/Ph.D. EE/CS preferred
- 10 or more years of experience in digital SoC development
- Industrial design experiences PCIE/JESD/Ethernet controller & PCS and respective SERDES PHY digital (PMA)
- Strong knowledge on CPU bus protocols and designs such as AXI/AHB/APB and DMA
- Solid design skill in Verilog / SystemVerilog RTL for complex SOC functional blocks in network products
- Solid experience in static timing analysis, defining timing constraints and exceptions
- Proficient in (Verilog/VHDL) and SystemVerilog RTL coding, LINT, CDC checking
- Experience bringing highly integrated mixed-signal SoCs to commercial mass production
- Experience with embedded systems, wireless protocols, power management, signal processing, and standard digital interfaces
- Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques
- Knowledge of languages such as C/C++, Perl, Tcl, and Python
- Strong communication and presentation skills
- Team player with a strong sense of urgency to complete projects on time
Benefits For Staff Engineer, ASIC Digital Design
- Comprehensive group health plan
- Matching 401(k)
- Training reimbursement
- Paid vacation
- Paid sick leave
- Paid holidays
- Maternity/paternity leave
- Jury duty leave
- Pre-IPO stock options
