ASIC DV Engineer, Simulation Acceleration and Hybrid Verification
Description For ASIC DV Engineer, Simulation Acceleration and Hybrid Verification
Meta is seeking an experienced ASIC Verification Engineer to join their Infrastructure organization, focusing on Simulation Acceleration and Hybrid Verification. This role is crucial for developing innovative ASIC solutions for Meta's data center applications. As a Design Verification Engineer, you'll be part of an elite team working on cutting-edge technology, responsible for verification closure of sub-systems and SoCs.
The position offers unique opportunities to collaborate with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams, all working towards achieving first-pass silicon success. You'll be instrumental in developing and implementing verification methodologies, working closely with architecture and design teams to ensure robust testing and validation of complex systems.
The role requires expertise in ASIC development, with hands-on experience in various programming languages and verification tools. You'll be working with state-of-the-art hardware platforms and be responsible for creating reusable verification environments. The position demands both technical excellence and strong collaborative skills, as you'll be interfacing with cross-functional teams and providing mentorship to other engineers.
Meta's commitment to pushing technological boundaries, especially in data center applications, makes this an exciting opportunity for someone passionate about hardware verification and innovation. The role offers exposure to cutting-edge technologies in AI/ML, networking, and high-speed interfaces, while working for a company that's shaping the future of digital connection and immersive experiences.
Responsibilities For ASIC DV Engineer, Simulation Acceleration and Hybrid Verification
- Propose, implement and promote the Simulation Acceleration and Hybrid Verification Methodology
- Work with Architecture and Design teams on functional, use case and performance test plans
- Define Verification scope, create environment, testplans and close use case scenarios
- Debug, root-cause and resolve functional failures in the design
- Develop and drive continuous Hybrid Verification improvements
- Build reusable/scalable environments for Hybrid Verification
- Provide training and mentoring for internal teams
Requirements For ASIC DV Engineer, Simulation Acceleration and Hybrid Verification
- Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
- 9+ years of relevant experience
- Track record of 'first-pass success' in ASIC development
- Experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification
- Experience with Zebu, Palladium, Veloce HW platforms
- Experience in Cluster and SoC level verification
- Proficiency in scripting languages (Python, Perl, TCL)
- Experience in architecting Hybrid Verification infrastructure
- Demonstrated experience with cross functional team collaboration
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