ASIC Engineer, Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization. This role focuses on developing innovative ASIC solutions for Meta's data center applications, particularly in IP and System On Chip (SoC) verification. The position offers a unique opportunity to work with cutting-edge technology in one of the world's leading tech companies.

As a Design Verification Engineer, you'll be part of an elite team working on critical hardware infrastructure. Your responsibilities will span from test-planning and UVM-based test bench development to verification closure. The role combines traditional simulation methods with advanced approaches like Formal and Emulation to ensure bug-free design implementation.

The position requires extensive experience in SystemVerilog/UVM methodology and hardware verification, making it ideal for seasoned professionals with a strong background in ASIC development. You'll have the opportunity to work with state-of-the-art tools and methodologies while collaborating with cross-functional teams including software, hardware, and post-silicon validation teams.

What makes this role particularly attractive is the chance to impact Meta's data center infrastructure directly. You'll be working on projects that power some of the world's most-used social platforms and next-generation technologies. The compensation package is highly competitive, including a base salary range of $173,000-$249,000, plus bonus, equity, and comprehensive benefits.

The role offers significant growth potential and the opportunity to work on challenging problems at scale. Meta's commitment to pushing technological boundaries, combined with their strong engineering culture, makes this an ideal position for someone looking to make a significant impact in hardware verification while working with some of the industry's best talents.