ASIC Engineer, Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization. This role focuses on building IP and System On Chip (SoC) solutions for data center applications. As a Design Verification Engineer, you'll be part of an innovative team working with industry leaders to develop cutting-edge ASIC solutions.

The position involves comprehensive verification responsibilities, from test-planning and UVM-based testbench development to verification closure. You'll utilize various approaches including traditional simulation, Formal methods, and Emulation to ensure bug-free designs. This role offers significant opportunities to collaborate across multiple teams, including full stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams.

Meta offers a competitive compensation package ranging from $212,000 to $291,000 annually, plus bonus and equity opportunities. The role requires deep expertise in SystemVerilog/UVM methodology with at least 15 years of hands-on experience. You'll be working on critical data center applications including Video, AI/ML, and Networking designs.

The ideal candidate will have extensive experience in IP/sub-system verification, strong debugging skills, and a proven track record of first-pass silicon success. Knowledge of advanced verification methodologies and tools is essential, as is the ability to work effectively with cross-functional teams.

Working at Meta means being part of a company that's shaping the future of digital connection, moving beyond traditional screens toward immersive experiences in AR and VR. This role offers the opportunity to contribute to groundbreaking technologies while working alongside some of the industry's best talent in either Sunnyvale, CA or Austin, TX.