ASIC Engineer, Design Verification
Description For ASIC Engineer, Design Verification
Meta is seeking an ASIC Design Verification Engineer to join their Infrastructure organization, focusing on building IP and System On Chip (SoC) solutions for data center applications. This role offers an exciting opportunity to work with cutting-edge technology in one of the world's leading tech companies.
As a Design Verification Engineer, you'll be part of a dynamic team working alongside industry experts to develop innovative ASIC solutions for Meta's data center applications. Your primary responsibilities will include verification closure of design modules and sub-systems, from test-planning to UVM-based test bench development. You'll utilize both traditional simulation methods and advanced approaches like Formal and Emulation to ensure bug-free designs.
The position offers significant opportunities for cross-functional collaboration, working with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams to achieve first-pass silicon success. This role is perfect for someone with strong verification experience who wants to impact Meta's infrastructure at scale.
The compensation package is competitive, ranging from $114,000 to $166,000 per year, plus bonus, equity, and comprehensive benefits. Meta offers a collaborative work environment and the chance to work on challenging problems that affect billions of users worldwide.
Key technical requirements include 3+ years of hands-on experience with SystemVerilog/UVM methodology or C/C++ based verification, proven track record in ASIC development cycles, and proficiency with EDA tools and scripting languages. The role requires a Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
Working at Meta means joining a company at the forefront of technology innovation, with a strong focus on the future of digital connection and communication. The company's commitment to pushing boundaries in hardware infrastructure makes this an exciting opportunity for someone passionate about ASIC design and verification.
Responsibilities For ASIC Engineer, Design Verification
- Define and implement block/IP/SoC verification plans, build verification test benches
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics
- Debug, root-cause and resolve functional failures in the design
- Collaborate with cross-functional teams towards ensuring highest design quality
Requirements For ASIC Engineer, Design Verification
- Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
- 3+ years hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
- Track record of 'first-pass success' in ASIC development cycles
- 3+ years experience in block/IP/sub-system and/or SoC level verification
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure
Benefits For ASIC Engineer, Design Verification
- Base salary + bonus + equity + benefits
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