ASIC Engineer, Memory Management Design Verification

Meta builds technologies that help people connect, find communities, and grow businesses, including Facebook, Messenger, Instagram, WhatsApp, and working on AR/VR experiences.
$173,000 - $249,000
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
10+ years of experience
AI

Description For ASIC Engineer, Memory Management Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization, focusing on building IP and System On Chip (SoC) solutions for data center applications. This role combines traditional hardware engineering with cutting-edge data center technology development.

The position offers an opportunity to work with industry leaders in ASIC development, where you'll be responsible for verification closure of design modules and sub-systems. The role encompasses the full spectrum of verification work, from test-planning to UVM-based test bench development and final verification closure. You'll utilize various approaches including traditional simulation, Formal methods, and Emulation to ensure design quality.

As a Design Verification Engineer, you'll be working on critical memory management systems, requiring deep expertise in SystemVerilog/UVM methodology and extensive experience with IP/sub-system verification. The role demands strong collaborative skills as you'll be working closely with full stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams.

The position offers competitive compensation ranging from $173,000 to $249,000 annually, plus bonus and equity opportunities. Meta provides a comprehensive benefits package and the chance to work on technology that impacts billions of users worldwide. The role is based in either Sunnyvale, CA or Austin, TX, offering the opportunity to work from major tech hubs.

This is an ideal position for a seasoned verification engineer with 10+ years of experience who wants to work on challenging problems in data center architecture while contributing to Meta's infrastructure development. The role requires both technical depth in verification methodologies and the ability to drive improvements in verification processes and technologies.

Working at Meta means being part of a company that's pushing the boundaries of social technology and moving beyond traditional 2D screens toward immersive experiences. You'll be contributing to the next evolution of social technology, helping to shape a future that goes beyond current digital connection capabilities.

Last updated 3 days ago

Responsibilities For ASIC Engineer, Memory Management Design Verification

  • Define and implement IP/SoC verification plans, build verification test benches
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined metrics
  • Debug, root-cause and resolve functional failures in the design
  • Collaborate with cross-functional teams
  • Develop and drive continuous Design Verification improvements

Requirements For ASIC Engineer, Memory Management Design Verification

Python
  • Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
  • 10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 10+ years experience in IP/sub-system and/or SoC level verification
  • Track record of 'first-pass success' in ASIC development cycles
  • Experience in SV Assertions, Formal, Emulation
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
  • Experience in architecting and implementing Design Verification infrastructure

Benefits For ASIC Engineer, Memory Management Design Verification

Medical Insurance
Equity
  • Bonus
  • Equity
  • Medical Insurance

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