ASIC Engineer, Physical Design
Description For ASIC Engineer, Physical Design
Meta is seeking an experienced ASIC Physical Design Engineer to join their Infrastructure organization. This role focuses on developing and implementing physical design solutions for advanced technology nodes, working with multi-hierarchy low-power and high-performance designs. The position requires expertise in backend implementation from Netlist to GDSII, with a focus on building efficient System on Chip (SoC) and IP for data center applications.
The ideal candidate will have extensive experience in physical design implementation, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, and static timing analysis. They should be capable of working with large SOC designs exceeding 100M gates and frequencies over 1GHZ. Knowledge of advanced technology nodes (5nm or below) and proficiency with industry-standard EDA tools is essential.
This role offers the opportunity to work at the cutting edge of hardware design at Meta, contributing to the infrastructure that powers some of the world's most widely-used social technology platforms. The position involves collaboration with cross-functional teams, IP vendors, and EDA tool vendors, requiring strong communication and technical leadership skills.
Key technical areas include low power implementation, power gating, multiple voltage rails, clock distribution networks, and physical verification in advanced nodes. The role also involves working with 3D-IC technology and advanced packaging solutions. This is an excellent opportunity for an experienced physical design engineer looking to make an impact on next-generation data center hardware infrastructure.
Meta offers a dynamic work environment where you'll be part of building technologies that connect billions of people worldwide. The company's commitment to innovation extends to its hardware infrastructure, making this role crucial for Meta's future technology development.
Responsibilities For ASIC Engineer, Physical Design
- Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs
- Resolve design and flow issues related to physical design
- Deliver physical design of end-to-end IP or integration of ASIC/SoC design
- Define and implement schemes to improve performance and power
- Work with RTL design team on partition architecture
- Interface with RTL design team to resolve congestion/timing issues
- Use EDA tool-based programming and scripting techniques
- Interact with tool vendors for fixes and improvements
Requirements For ASIC Engineer, Physical Design
- Experience in physical design and timing closure
- Bachelor's degree in Computer Science, Computer Engineering or relevant field
- Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below
- Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime
- Hands-on experience in SoC floor planning and high-frequency designs
- Knowledge of geometry/process/device technology implications
- Experience with large SOC designs (>100M gates) with frequencies over 1GHZ
- 10+ years of experience in interpersonal and teamwork
- Programming/scripting skills: TCL, Python, Perl or Shell
Jobs Related To Meta ASIC Engineer, Physical Design
