ASIC Engineer, Physical Design
Description For ASIC Engineer, Physical Design
Meta is seeking an ASIC Physical Design Engineer for their Infrastructure organization to work on cutting-edge System on Chip (SoC) and IP development for data center applications. This role combines deep technical expertise in physical design implementation with strategic thinking about power and performance optimization. The position involves working with advanced technology nodes (5nm and below) and requires mastery of the complete physical design flow from Netlist to GDSII.
The ideal candidate will be responsible for implementing complex multi-hierarchy designs, managing physical design workflows, and collaborating with RTL teams to optimize designs early in the development cycle. They will need to balance performance and power requirements while working with large-scale SOC designs exceeding 100M gates and frequencies over 1GHz.
This role offers the opportunity to work with state-of-the-art EDA tools and contribute to Meta's infrastructure development. The position requires both technical depth in ASIC design and strong communication skills to work effectively with cross-functional teams and vendors. The successful candidate will play a crucial role in developing next-generation hardware solutions for Meta's data center infrastructure.
Working at Meta means joining a company at the forefront of social technology and contributing to products that connect billions of people worldwide. The company offers a collaborative environment, comprehensive benefits, and the chance to work on challenging technical problems at scale. This role is based in Bangalore, India, and offers the opportunity to work with a global team of experts in hardware design and development.
Responsibilities For ASIC Engineer, Physical Design
- Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs
- Resolve design and flow issues related to physical design
- Deliver physical design of end-to-end IP or integration of ASIC/SoC design
- Define and implement schemes to improve performance and power
- Work with RTL design team on partition architecture
- Interface with RTL design team for design modifications
- Use EDA tool-based programming and scripting
- Interact with tool vendors for fixes and improvements
Requirements For ASIC Engineer, Physical Design
- Experience in physical design and timing closure
- Bachelor's degree in Computer Science, Computer Engineering or relevant field
- Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below
- Experience with EDA tools
- Hands-on experience in SoC floor planning
- Knowledge of geometry/process/device technology
- Experience with large SOC designs
- 10+ years of experience in interpersonal and teamwork
- Programming/scripting skills: TCL, Python, Perl or Shell
Benefits For ASIC Engineer, Physical Design
- Equal Employment Opportunity
- Reasonable accommodations for disabilities
- Pregnancy-related support
Jobs Related To Meta ASIC Engineer, Physical Design
