ASIC Implementation Engineer - Timing
Description For ASIC Implementation Engineer - Timing
Meta is seeking an experienced ASIC Implementation Engineer - Timing to join their Infrastructure organization. This role is crucial in developing and implementing timing solutions for System on Chip (SoC) and IP designs targeted for data center applications. The position combines technical expertise in front-end implementation, from RTL to netlist, with a focus on timing constraints and synthesis.
The role requires deep expertise in timing analysis, constraint development, and optimization techniques. You'll be working with cutting-edge technology, developing solutions for Meta's data center infrastructure, and collaborating with cross-functional teams including Design Engineers, DV Engineers, and Physical Design Engineers.
As an ASIC Implementation Engineer, you'll be responsible for developing timing constraints, performing static timing analysis, and optimizing designs for timing, area, and power. The role involves working with advanced tools and methodologies, including PrimeTime-STA, Logic/Physical Synthesis, and various automation scripts.
Meta offers a competitive compensation package ranging from $142,000 to $203,000 per year, plus bonus, equity, and comprehensive benefits. The position is available in either Sunnyvale, CA or Austin, TX, offering the opportunity to work with one of the world's leading technology companies that's shaping the future of social connection and virtual reality.
The ideal candidate will bring at least 5 years of experience with STA tools, strong knowledge of ASIC flows, and excellent communication skills. This is an excellent opportunity for someone looking to work on challenging technical problems while contributing to Meta's infrastructure development.
Responsibilities For ASIC Implementation Engineer - Timing
- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level including SOC
- Analyze inter-block timing and develop IO budgets for partition blocks
- Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes
- Perform STA for full chip and Physical partition blocks using PrimeTime
- Run Logic/Physical Synthesis using advanced optimization techniques
- Develop Automation scripts and Methodology for FE-tools
- Work with Design Engineers, DV Engineers, and Emulation Engineers
- Interact with Physical Design Engineers for timing feedback
Requirements For ASIC Implementation Engineer - Timing
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 5+ years of experience with STA tools
- Experience with developing full chip flat & hierarchical timing constraints
- Experience with AOCV/POCV timing analysis, SI noise analysis
- Experience with running Static Timing Analysis for full chip using DMSA
- Knowledge of front-end and back-end ASIC flows
- Experience with communicating across functional internal teams and vendors
Benefits For ASIC Implementation Engineer - Timing
- Salary + bonus + equity + benefits
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