Design Verification Engineer
Description For Design Verification Engineer
Meta's Reality Labs (RL) is seeking a Design Verification Engineer to join their innovative AR/VR team. This role sits at the intersection of hardware and software, focusing on custom silicon development for augmented reality devices. As a Design Verification Engineer, you'll work with world-class researchers and engineers to implement testing infrastructure for new core IP implementations and contribute to state-of-the-art vision and sensing algorithms.
The position requires expertise in digital design and verification, with a focus on SystemVerilog, UVM methodology, and hardware validation. You'll be responsible for creating comprehensive test plans, driving verification closure, and ensuring the highest quality standards for Meta's AR hardware initiatives. The role offers an opportunity to work on breakthrough technology in computer vision, machine learning, mixed reality, and graphics.
This is an excellent opportunity for an experienced verification engineer who wants to make an impact in the future of AR/VR technology. You'll be working in Sunnyvale, CA, with competitive compensation ranging from $142,000 to $203,000 annually, plus bonus and equity benefits. The position requires 5+ years of relevant experience and offers the chance to work with cutting-edge technology while collaborating with cross-functional teams.
Meta's commitment to pushing the boundaries of what's possible in AR/VR, combined with their comprehensive benefits package and innovative work environment, makes this an exciting opportunity for someone passionate about hardware verification and next-generation computing platforms. You'll be part of a team that's literally building the future of human-computer interaction through advanced silicon development.
Responsibilities For Design Verification Engineer
- Work with researchers and architects defining verification plans for each of the different core IP
- Define and track detailed test plans for the different modules and top levels
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams
- Develop and drive continuous Design Verification improvements using the latest verification methodologies
Requirements For Design Verification Engineer
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- 5+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology
- Track record of 'first-pass success' in ASIC development cycles
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure
Benefits For Design Verification Engineer
- Bonus
- Equity
- Medical benefits
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