Senior Silicon Design Library Verification Engineer

Microsoft's Silicon Engineering and Solutions Team is seeking a Senior Silicon Design Library Verification Engineer to join their Central Front-End Tools, Flows and Methodology (TFM) group in Bangalore. This role combines hardware engineering expertise with software development, focusing on developing and maintaining verification infrastructure for silicon design.

The position requires deep expertise in front-end digital design and verification, with emphasis on working with Verilog/SV/UVM based IP development. You'll be responsible for driving common front-end methodologies for SoC and IP design, managing global design/verification library components, and ensuring quality through various verification processes.

As a senior engineer, you'll provide technical leadership to the design community, work closely with stakeholders across Microsoft Silicon group, and collaborate with EDA vendors to optimize solutions for silicon verification and design. The role offers an opportunity to work on cutting-edge silicon technology while mentoring junior team members.

The ideal candidate should have at least 6 years of experience, strong background in VLSI design cycle, and expertise in design compilation, simulation tools and flows. This position offers a hybrid work environment with up to 50% work from home flexibility, comprehensive benefits including industry-leading healthcare, educational resources, and various other perks.

This is an excellent opportunity for someone passionate about silicon design and verification to work on innovative projects at Microsoft, one of the world's leading technology companies, while contributing to the development of next-generation silicon solutions.