Senior Mask Layout Design Engineer

NVIDIA is the world leader in accelerated computing, pioneering AI and digital twins technology to transform industries.
Hsinchu, North District, Hsinchu City, TaiwanTaipei City, Taiwan
Embedded
Senior Software Engineer
Hybrid
5,000+ Employees
5+ years of experience
AI · Enterprise SaaS

Description For Senior Mask Layout Design Engineer

NVIDIA, the world leader in accelerated computing, is seeking a Senior Mask Layout Design Engineer to join their growing team. This role is perfect for someone passionate about handling challenging high-speed mixed-signal circuit designs. NVIDIA has a rich history of innovation, from inventing the GPU in 1999 to revolutionizing AI through GPU deep learning. The company continues to evolve by tackling complex challenges that impact the world.

As a Senior Mask Layout Design Engineer, you'll be working with cutting-edge sub-micron CMOS FinFET technologies, using Cadence tools to create physical layouts for mixed-signal functions including PLLs, high-speed memory I/O circuits, SerDes, and ESD structures. You'll collaborate closely with ASIC and mixed-signal engineers, contributing to the development of next-generation NVIDIA products.

The ideal candidate brings 5+ years of mask design experience, deep knowledge of analog circuit layout concepts, and expertise in Cadence custom circuit design tools. Your strong technical foundation will be complemented by your ability to work effectively in a team environment and communicate clearly in English. This position offers the opportunity to work at the forefront of technology, contributing to NVIDIA's mission of amplifying human creativity and intelligence through innovative computing solutions.

Working at NVIDIA means joining a company that values diversity and maintains an inclusive environment. The hybrid work arrangement provides flexibility while maintaining collaborative opportunities with talented colleagues in Hsinchu or Taipei, Taiwan.

Last updated 7 hours ago

Responsibilities For Senior Mask Layout Design Engineer

  • Perform physical layout for mixed-signal functions in sub-micron CMOS FinFET technologies using Cadence tools
  • Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
  • Floor planning, custom layout and verifying against design rules and schematics

Requirements For Senior Mask Layout Design Engineer

Python
  • BSEE with a minimum of 5 years of relevant mask design / layout experience
  • Understanding of analog circuit layout concepts in submicron CMOS technologies
  • Expert with Cadence custom circuit design tools - particularly virtuoso
  • Experience with DRC and LVS verification tools
  • Able to communicate in spoken and written English
  • Work effectively in a team, good interpersonal skills
  • Proficiency in scripting languages like perl, python, skill
  • Knowledge of DRC and LVS checking flows

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