Senior Timing Methodology Engineer
Description For Senior Timing Methodology Engineer
NVIDIA, a pioneer in GPU technology and AI innovation, is seeking a Senior Timing Methodology Engineer to drive sign-off strategies for world-leading GPUs and SoCs. This role represents a unique opportunity to shape the future of computing across multiple product lines, from consumer graphics to self-driving cars and AI applications. The position focuses on optimizing performance, yield, and reliability through comprehensive modeling and analysis at advanced technology nodes as deep as 5nm and beyond.
The role combines technical expertise in ASIC design and timing with strategic thinking to develop sophisticated sign-off methodologies. You'll work with cutting-edge technology, collaborating with industry experts to push the boundaries of what's possible in semiconductor design. The position requires deep understanding of circuit modeling, device physics, and modern design challenges like deep submicron effects, aging, and thermal impacts.
This is an ideal opportunity for someone passionate about precision engineering at the nanoscale, where your work will directly influence the next generation of computing platforms. You'll be part of a highly motivated team at NVIDIA, known for continuously reinventing itself and driving innovation in graphics, AI, and parallel computing.
The role offers competitive compensation with a base salary range of $136,000 to $264,500, plus equity and benefits. You'll be working at one of technology's most desirable employers, contributing to projects that matter to the world while advancing your career in semiconductor design and methodology development.
Responsibilities For Senior Timing Methodology Engineer
- Improve and validate flows for Prime-Time, Prime-Shield and Tempus STA QoR metrics for sign-off flow
- Develop custom flows for validating QoR of ETM models
- Develop flows/recommendations on STA sign-off to model deep submicron physical effects
- Collaborate with technology leads, VLSI physical design, and timing engineers
- Develop tools and methodologies to improve design performance
- Work on various aspects of STA, constraints, timing and power optimization
Requirements For Senior Timing Methodology Engineer
- MS (or equivalent experience) in Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing
- Good understanding of modeling circuits for sign-off
- Good knowledge of extraction, device physics, STA methodology and EDA tools limitations
- Understanding of 3DIC, stacking, packing, self-heating and its impact on timing/STA closure
- Understanding crosstalk, electro-migration, noise, OCV, timing margins
- Expertise in coding- TCL, Python. C++ is a plus
- Strong communications skill and good standout colleague
Benefits For Senior Timing Methodology Engineer
- Equity
- Medical Insurance
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