ASIC Design Engineer, Low Power AI Subsystems
Description For ASIC Design Engineer, Low Power AI Subsystems
Qualcomm Technologies is seeking an ASIC Design Engineer to join their team working on cutting-edge low power AI subsystems for audio products. This role focuses on designing ultra-low power subsystems within SoCs, specifically for audio and context-aware applications. The position involves working with multiple always-on IPs and solving complex power domain challenges.
The role is perfect for engineers passionate about hardware design who want to push the boundaries of AI and audio technology. You'll be working on premium wireless connectivity solutions, focusing on high integration levels and immersive sound quality. The position offers significant opportunities for innovation, particularly in minimizing power consumption while maintaining high performance.
As part of Qualcomm's team, you'll be involved in groundbreaking projects that combine AI with audio processing, working on solutions that haven't been done before. The role requires a blend of technical expertise in ASIC design and creative problem-solving skills. You'll be working with state-of-the-art design tools and collaborating with global teams to develop next-generation audio solutions.
The ideal candidate should have experience with ASIC hardware design, proficiency in RTL design languages, and a strong understanding of VLSI concepts. This position offers excellent growth opportunities and the chance to make a significant impact on Qualcomm's audio technology portfolio. You'll be at the forefront of developing innovative solutions that shape the future of low-power AI subsystems and smart audio applications.
Responsibilities For ASIC Design Engineer, Low Power AI Subsystems
- Design high speed, low power digital hardware solutions
- Contribute to definition, micro-architecture and documentation
- Collaborate with Verification team to test, debug and close coverage on the design
- Evaluate synthesis results to verify design meets speed, power and area targets
- Support internal hardware integration and SW teams around the world
- Resolve architecture, design, or verification problems
- Use various design tools to check and improve design quality
- Provide ideas and further innovation of ASICs, IP cores, and process flows
Requirements For ASIC Design Engineer, Low Power AI Subsystems
- Professional or academic ASIC hardware design and/or implementation experience
- Proficiency with Verilog/VHDL RTL design languages
- Good understanding of ASIC/VLSI concepts
- Experience in logic synthesis using Synopsis and/or Cadence tools
- 2+ years of ASIC hardware design related experience preferred
- Working knowledge of UPF specification preferred
- Experience with clock domain crossing techniques preferred
- Scripting skills (Python, PERL, TCL or C) preferred
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