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ASIC RTL Design Engineer (Display) - Sr Lead

A global leader in wireless technology innovation and the development of semiconductors and mobile technologies.
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
4+ years of experience
Hardware
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Description For ASIC RTL Design Engineer (Display) - Sr Lead

Qualcomm, a global leader in wireless technology and semiconductor innovation, is seeking a Senior Lead ASIC RTL Design Engineer to join their Display team in Bangalore. This role offers an exciting opportunity to work on cutting-edge display subsystems for various Qualcomm business units including VR, AR, Compute, IOT, and Mobile platforms.

The position requires a skilled professional with 4+ years of RTL Design experience and a strong background in ASIC development. You'll be responsible for leading front-end design activities, working with RTL coding, and implementing complex display subsystems. The role demands expertise in various technical areas including Verilog/VHDL/System Verilog, micro-architecture design, and various verification methodologies.

As a Senior Lead, you'll collaborate with cross-functional teams across different time zones, working on performance and power management strategies for product roadmaps. The position offers exposure to cutting-edge technology in the semiconductor industry, working alongside some of the most respected engineering experts in the field.

Qualcomm offers comprehensive benefits including world-class health coverage, financial planning programs, and continuous learning opportunities through tuition reimbursement and mentorship programs. The company fosters a supportive, inclusive culture where innovative ideas are valued and career growth is prioritized.

This role is perfect for someone who wants to be at the forefront of hardware engineering, working on technologies that power next-generation devices while having access to professional development opportunities and competitive benefits.

Last updated 2 days ago

Responsibilities For ASIC RTL Design Engineer (Display) - Sr Lead

  • Design and lead Front-end design activities for Display Sub-system
  • Perform RTL design, simulation, synthesis, timing analysis, and various checks
  • Work with technology/circuit design team to close IP block specifications
  • Collaborate with verification/physical design team
  • Support SoC team to integrate Display Sub-system IP solution
  • Work with system/software/test team on low power features
  • Evaluate new low-power technologies
  • Perform block & chip-level performance analysis

Requirements For ASIC RTL Design Engineer (Display) - Sr Lead

Python
  • Bachelor's/Master's degree in Electronics & Telecom Engineering, Microelectronics, Computer Science, or related field
  • 4+ years RTL Design/Hardware Engineering experience
  • Strong Domain Knowledge on RTL Design, implementation, and integration
  • Experience with RTL coding using Verilog/VHDL/System Verilog
  • Experience in micro-architecture & designing cores and ASICs
  • Familiar with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs
  • Exposure in scripting (Pearl/Python/TCL)
  • Strong debugging capabilities
  • Good team player

Benefits For ASIC RTL Design Engineer (Display) - Sr Lead

Medical Insurance
401k
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and future preparation programs
  • Emotional/mental strength and resilience support
  • Comprehensive wellbeing programs
  • Tuition reimbursement
  • Mentorship programs

Interested in this job?