EVA/Video Design Verification Engineer

A global technology company specializing in semiconductor and telecommunications equipment.
Cork, Ireland
Embedded
Mid-Level Software Engineer
Hybrid
5,000+ Employees
2+ years of experience
AI

Description For EVA/Video Design Verification Engineer

Qualcomm is seeking a EVA/Video Design Verification Engineer for their state-of-the-art facility in Cork, Ireland. This role is part of the Multimedia Video and Computer Vision HW Design team, focusing on developing complex IP Cores for cutting-edge Video CODEC Standards and Advanced Computer Vision applications. The position offers a hybrid work arrangement, combining work from home with time in their new Penrose Dock office. The ideal candidate will have strong experience in verification technologies, SOC systems, and firmware development. The role involves collaborating with various teams, from architecture to post-silicon validation, and requires expertise in System Verilog/UVM, C++, and Python. Qualcomm provides an excellent benefits package including stock options, comprehensive insurance, and work-life balance initiatives. Cork offers an exceptional quality of life, with strong international connections and a thriving tech community. The company emphasizes employee well-being and provides numerous opportunities for professional growth and development.

Last updated 7 hours ago

Responsibilities For EVA/Video Design Verification Engineer

  • Architect, design, and implement testbench to verify structure and performance of computer vision IPs
  • Create and maintain verification test benches and environments in System Verilog/UVM
  • Collaborate with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams
  • Participate in micro-architecture reviews
  • Execute system level test content including directed testcases
  • Build automation for continuous integration and testing
  • Write technical documentation and feature descriptions
  • Perform scripting and automation tasks

Requirements For EVA/Video Design Verification Engineer

Python
  • Minimum 2 years of DV experience using uvm/assertion based verification technologies
  • Experience in verifying complex SOC or SOC subsystems
  • Experience with caches and DDR memory protocol verification
  • Exposure to firmware/driver development using C++
  • Exposure to successful tapeouts from conception to post silicon debug
  • Exposure to Formal verification
  • Experience with Power aware simulations
  • Experience with perf and power verification
  • Experience with Gate level Simulations
  • Proficiency in UVM, system verilog, assertion, C++, python, Power Aware simulations

Benefits For EVA/Video Design Verification Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Education Budget
Equity
Parental Leave
Relocation Benefits
  • Salary, stock and performance related bonus
  • Maternity/Paternity Leave
  • Employee stock purchase scheme
  • Matching pension scheme
  • Education Assistance
  • Relocation and immigration support
  • Life, Medical, Income and Travel Insurance
  • Subsidised memberships for physical and mental well-being
  • Bicycle purchase scheme
  • Employee run clubs

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