IC Package Layout Engineer, Up to Senior Staff

Qualcomm is a company of inventors that unlocked 5G, transforming industries and creating new possibilities in connectivity.
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Staff Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Enterprise SaaS

Description For IC Package Layout Engineer, Up to Senior Staff

Qualcomm is seeking a talented IC Package Layout Engineer to join their team in Hsinchu City, Taiwan. This role offers an exciting opportunity to work at the forefront of 5G technology and semiconductor innovation. As an IC Package Layout Engineer, you'll be responsible for driving advanced package selection, physical design, and optimization of next-generation products.

The position requires expertise in package/SIP physical design, layout, and tape-out processes, working closely with cross-functional teams to achieve optimal mechanical, electrical, and thermal performance. You'll be implementing physical designs for SoC packages and modules while ensuring compliance with SI/PI requirements.

The ideal candidate brings 5+ years of experience and strong proficiency in Cadence APD & SiP tools, along with deep knowledge of IC packaging structures and high-speed interfaces. This role offers growth opportunities within Qualcomm's innovative environment, where you'll work alongside leading engineering experts.

Qualcomm provides comprehensive benefits including world-class health coverage, financial planning support, and professional development through tuition reimbursement and mentorship programs. The company's culture emphasizes work-life balance with wellbeing programs and emotional/mental health support.

This position is perfect for someone passionate about semiconductor technology who wants to contribute to world-changing innovations while developing their career at a global technology leader. You'll be part of a team that's shaping the future of connectivity and mobile technology.

Last updated 32 minutes ago

Responsibilities For IC Package Layout Engineer, Up to Senior Staff

  • Own and drive advanced package selection, new generation product package structure, and configuration optimization
  • Responsible for Package/SIP physical design and layout, optimization, DV, and tape out
  • Work with multi-functional teams to achieve optimized mechanical, electrical, and thermal performance
  • Implement the physical design of packages and modules for SoC
  • Interface and coordinate with multi-functional groups on new product package/SiP feasibility analysis
  • Define and develop design verification and automation strategy
  • Work multi-functionally to optimize package pin out
  • Ensure package design is optimized with SI/PI requirements

Requirements For IC Package Layout Engineer, Up to Senior Staff

Kubernetes
  • Bachelor's or Master's degree in electrical engineering, mechanical engineering, material science, or related fields
  • 5+ years of experience
  • Proficient in Cadence APD & SiP
  • Basic knowledge in high-speed IO interfaces and electromagnetic field
  • Knowledge of IC packaging structures
  • Experience in package design and proficiency in Cadence Allegro platform tools
  • Basic understanding of SI/PI tools
  • Knowledge of high-speed layout constraints
  • Solid understanding of Design Rules Check and Design for Manufacturing

Benefits For IC Package Layout Engineer, Up to Senior Staff

Medical Insurance
401k
Education Budget
  • World-class health benefit coverage
  • Financial future preparation programs
  • Emotional/mental strength support
  • Wellbeing programs
  • Tuition reimbursement
  • Mentorship programs

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