Memory Subsystem Performance Architect

A global leader in wireless technology innovation and semiconductor development.
$115,600 - $173,400
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
2+ years of experience
Enterprise SaaS

Description For Memory Subsystem Performance Architect

Join Qualcomm's Infrastructure IP Team as a Memory Subsystem Performance Architect, where you'll be part of a multi-disciplinary group focused on defining and designing Platform infrastructure HW components. This role combines technical expertise in memory systems with performance optimization, requiring deep understanding of system architecture and analytical skills.

The position involves working with cutting-edge memory technologies and system architecture, focusing on performance analysis and optimization of memory controllers, system cache, and interconnect components implemented in Qualcomm's SoCs. You'll conduct sophisticated performance analyses using cycle-accurate models, identify bottlenecks, and drive improvements in system performance.

As a key member of the team, you'll collaborate with IP designers, Design Verification teams, and System performance architects, contributing to Qualcomm's leadership in mobile and computing technology. The role offers exposure to next-generation memory technologies and the opportunity to influence the architecture of future Qualcomm products.

The position offers competitive compensation ($115,600 - $173,400) plus comprehensive benefits including annual bonuses, RSU grants, and extensive professional development opportunities. You'll work in San Diego, California, joining a team known for innovation in semiconductor technology.

This role is ideal for someone with strong technical skills in computer architecture, particularly memory systems, combined with analytical capabilities and programming expertise in C++ and Python. You'll have the opportunity to work on challenging problems while contributing to products that impact millions of devices worldwide.

Last updated 5 hours ago

Responsibilities For Memory Subsystem Performance Architect

  • Modeling and analysis of system cache, memory controller scheduling algorithms, and features
  • Develop tests, testplans and testing infrastructure for new architecture/features
  • Conduct in-depth analysis of product requirement dashboards
  • Analyze CPU and GPU benchmarks to identify memory bottlenecks
  • Mentor young engineers and encourage good coding practices
  • Drive model development best practices and process automations

Requirements For Memory Subsystem Performance Architect

Python
  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design experience
  • Sound understanding of System interconnect, Caches and Memory Technologies
  • Good understanding of QoS concepts
  • Good handle in Object oriented programming and C++
  • Strong scripting skills (Perl/Python)
  • Experience with data analysis using Excel, R, Python
  • Self-driven, methodical and process oriented
  • Excellent oral and written communication

Benefits For Memory Subsystem Performance Architect

Medical Insurance
401k
Equity
  • Competitive annual discretionary bonus
  • RSU grants
  • Comprehensive health coverage
  • Education and development programs
  • Tuition reimbursement
  • Mentorship programs

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