Sensor Subsystem Design Verification Engineer
Description For Sensor Subsystem Design Verification Engineer
Qualcomm is seeking a Sensor Subsystem Design Verification Engineer to join their team in Cork, Ireland. This role offers an exciting opportunity to work with cutting-edge sensor technologies embedded in smartphones, automotive systems, IoT devices, smartwatches, and other consumer electronics.
The position involves working on ASIC design verification processes, from test planning to environment development using UVM, managing regressions, and conducting coverage analysis to meet Qualcomm's quality metrics for tapeout. You'll collaborate with system architects, design teams, and software engineers to verify designs specific to Digital Sensor subsystems for integration into SoC for mobile applications.
As a member of Qualcomm's engineering team, you'll be working for a global leader in semiconductor and telecommunications technology. The company offers comprehensive benefits including stock options, performance bonuses, health coverage, and educational assistance. Cork, as Ireland's second-largest economic center, provides an excellent quality of life and is home to a diverse, international community.
The ideal candidate should have a bachelor's degree in Engineering or related field with 2+ years of ASIC design verification experience. Strong knowledge of UVM, SystemVerilog, and Python/Perl scripting is essential. You'll need excellent analytical and communication skills, as you'll be working in a dynamic, fast-paced team environment.
This role is perfect for someone who wants to work at the forefront of sensor technology while being part of a company that's driving innovation in mobile computing, AI, and IoT. You'll have the opportunity to work on projects that impact millions of devices worldwide while developing your skills in a supportive, technology-driven environment.
The position offers competitive compensation, comprehensive benefits, and the chance to work in a modern, collaborative workspace. Qualcomm's strong focus on employee development, work-life balance, and inclusive culture makes this an excellent opportunity for engineers looking to advance their careers in semiconductor design verification.
Responsibilities For Sensor Subsystem Design Verification Engineer
- Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
- Developing Testbenches and Verification Components
- Test plan development based on Design documents
- Writing and debugging SystemVerilog assertions
- Analysing coverage data and working with Design teams
- Develop/augment framework for running regressions
- Running/Debugging Power aware simulations
- Support integration of design in higher-level subsystem
- Python/Perl automation for improving workflows
- Supporting software and other teams with debug
- Documentation
Requirements For Sensor Subsystem Design Verification Engineer
- Bachelor's degree in Science, Engineering, or related field
- ASIC design verification, UVM-based functional verification experience
- Experience with constrained-random verification environment
- Experience with System Verilog Assertions
- Extensive usage of RTL simulation tools
- UVM, System Verilog, Perl/Python shell-scripting skills
- Familiarity with C/C++
- Strong analytical and multitasking skills
- Excellent written and verbal skills
- Strong interpersonal skills
Benefits For Sensor Subsystem Design Verification Engineer
- Salary, stock and performance related bonus
- Maternity/Paternity Leave
- Employee stock purchase scheme
- Matching pension scheme
- Education Assistance
- Relocation and immigration support
- Life, Medical, Income and Travel Insurance
- Subsidised memberships for physical and mental well-being
- Bicycle purchase scheme
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