Staff ASIC Design Engineer
Description For Staff ASIC Design Engineer
Qualcomm, a pioneering technology innovator, is seeking a Staff ASIC Design Engineer to join their team in Noida, India. This role represents an exciting opportunity to work at the forefront of hardware engineering, developing cutting-edge solutions that shape the future of digital transformation.
As a Staff ASIC Design Engineer, you'll be responsible for planning, designing, optimizing, and testing electronic systems, with a focus on micro-architecture development and RTL digital design. The role requires expertise in front-end flows, DDR protocols, and system architecture, combining technical depth with leadership responsibilities.
The position offers the chance to work with cross-functional teams across the globe, leading junior engineers while contributing to groundbreaking products. You'll be involved in various aspects of the development process, from initial architecture consultation to system integration and debugging.
The ideal candidate brings 7-12 years of ASIC design experience, with strong fundamentals in digital design and system architecture. This role provides an opportunity to work with state-of-the-art technology while contributing to Qualcomm's mission of enabling a smarter, connected future.
Working at Qualcomm means being part of a team that pushes the boundaries of what's possible in technology. You'll have the opportunity to work on projects that impact next-generation experiences, collaborating with talented professionals across the organization. The role offers both technical challenges and leadership opportunities, making it ideal for experienced engineers looking to advance their careers in hardware design.
Responsibilities For Staff ASIC Design Engineer
- Micro architecture & RTL development in consultation with Architecture and Systems teams
- RTL Front-end quality checks
- Work with functional verification team on test-plan development and waveform debugs
- Hands on experience in constraint development and timing closure
- PPA efficient design and low power checks
- Support performance debugs and address performance bottlenecks
- Provide support to sub-system, SoC integration and chip level debug
Requirements For Staff ASIC Design Engineer
- MTech/BTech in EE/CS with 7-12 years of ASIC Design experience
- Strong fundamentals and experience in micro-architecture development and RTL Digital design
- Exposure to front-end flows (Lint, CDC, low-power checks, Synth etc.)
- Domain knowledge in LP/PC DDR 2/3/4/5
- Understanding of protocols like AXI/ACE/CHI/AHB
- Good communication skills
- Experience working with global teams
- Experience with post-silicon bring-up and debug is a plus
- Ability to lead/guide junior engineers
- Flexibility to contribute in various capacities beyond RTL design
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