Sr. Design Verification Engineer (Silicon Engineering)
Description For Sr. Design Verification Engineer (Silicon Engineering)
SpaceX is seeking a Senior Design Verification Engineer to join their Silicon Engineering team in Redmond, WA. This role is crucial in developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe, specifically supporting the Starlink satellite constellation project.
The position offers an opportunity to work alongside world-class cross-disciplinary teams in systems, firmware, architecture, design, validation, and product engineering. The successful candidate will be responsible for developing and verifying complex digital designs that enable connectivity in previously underserved areas, directly contributing to SpaceX's mission of making reliable internet accessible globally through Starlink.
The role requires a strong background in digital ASIC and FPGA verification, with responsibilities spanning from writing test plans to post-silicon validation. Candidates should have at least 8 years of experience and a bachelor's degree in electrical or computer engineering. The position demands expertise in verification methodologies, strong programming skills, and experience with tools like UVM/OVM/VMM.
SpaceX offers a competitive compensation package ranging from $160,000 to $220,000 per year, complemented by comprehensive benefits including medical coverage, 401(k), stock options, and various insurance benefits. The company culture emphasizes innovation, technical excellence, and a commitment to advancing space technology.
This role presents a unique opportunity to contribute to SpaceX's ambitious goals of revolutionizing space technology and global communications infrastructure. The successful candidate will be part of a team working on technology that is literally changing how the world connects, while also supporting SpaceX's ultimate mission of enabling human life on Mars.
Responsibilities For Sr. Design Verification Engineer (Silicon Engineering)
- Responsible for digital ASIC and/or FPGA verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
- Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs
Requirements For Sr. Design Verification Engineer (Silicon Engineering)
- Bachelor's degree in electrical engineering or computer engineering
- 8+ years of experience with design verification and test bench development
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- Strong problem-solving and coding skills
- Experience in constrained random verification
- Expertise in developing test plans, implementing coverage models, and analyzing results
- Experience with scripting languages, e.g. Python for automation
- RTL design, chip bring-up, and post-silicon validation experience
- Ability to work in a dynamic environment with changing needs and requirements
- Must be willing to work extended hours and weekends as needed
Benefits For Sr. Design Verification Engineer (Silicon Engineering)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
- Stock options
- Employee Stock Purchase Plan
- Long-term incentives
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