DFT Engineer
Description For DFT Engineer
Broadcom's ASIC Product Division is seeking a Principal DFT Engineer to lead their Design for Testability initiatives at their San Jose facility. This role combines hardware engineering with software development, requiring expertise in both digital/analog circuit design and programming. The position offers a competitive salary range of $119,000 - $190,000, along with comprehensive benefits including medical coverage, 401(k) matching, and equity compensation.
The role demands a unique blend of technical expertise in Design for Testability (DFT), requiring the successful candidate to lead complex programs from specification through implementation and verification. You'll be working with cutting-edge technology at 7nm and beyond, implementing various testing methodologies including Scan, MBIST, and LBIST, while also developing automation solutions using languages like Python, Ruby, and TCL.
What makes this role particularly exciting is the opportunity to work on advanced semiconductor technologies while collaborating with global teams and directly interfacing with customers. The position offers significant technical challenges in silicon testing and validation, requiring innovative solutions for complex testability problems. The comprehensive benefits package, including equity participation and discretionary bonuses, makes this an attractive opportunity for experienced DFT engineers looking to make an impact at a global technology leader.
Broadcom's position as a leading semiconductor company provides stability and opportunities for growth, while the technical challenges of working with advanced node technologies offer continuous learning opportunities. The role combines hands-on technical work with leadership responsibilities, making it ideal for someone who enjoys both technical depth and project leadership.
Responsibilities For DFT Engineer
- Lead DFT programs from specification to implementation and verification
- Define DFT specifications for ASICs based on requirements
- Implement DFT including Scan, MBIST, TAP, LBIST, IO, SerDes integration
- Work with STA and DI Engineers for design closure
- Generate, verify and debug test vectors
- Validate vectors on ATE during silicon bring up
- Assist with silicon failure analysis and yield improvement
- Interface with customer and global engineering teams
- Debug customer returned parts on ATE
- Innovate DFT solutions for 7nm & beyond
- Automate DFT & Test Vector Generation flows
Requirements For DFT Engineer
- Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of experience or Masters with 6+ years experience
- Strong DFT background (IO and Analog DFT, ATPG, Scan, BIST)
- Experience with scan insertion and compression (DFT Compiler, Mentor TestKompress)
- Verilog coding, testbench generation & simulation experience
- Memory BIST insertion and verification experience
- Knowledge of IEEE1149.1 and IEEE1149.6
- Strong background in IEE1687, IJTAG, ICL and PDL
- Solid knowledge in analog and digital circuit design
- Understanding of Si processing and transistor reliability principles
- Excellent problem solving and communication skills
- Programming skills in TCL, PERL, RUBY, PYTHON, C++ or similar
Benefits For DFT Engineer
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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