Mixed-Signal Design Verification and Validation Engineer
Description For Mixed-Signal Design Verification and Validation Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior Mixed-Signal Design Verification and Validation Engineer for their San Jose office. This is a highly visible role focused on ASIC development for data center connectivity applications.
The position requires extensive experience in mixed-signal design verification, with candidates needing either 8+ years of experience with a BSc or 6+ years with an MSc in Electrical or Computer Engineering. The role demands expertise in various technical areas including SV UVM, verification coverage matrix, and hands-on experience with industry-standard EDA tools from Synopsys/Cadence.
The ideal candidate will have deep knowledge of analog mixed-signal building blocks such as ADCs, DACs, PLLs, and SerDes, along with experience in DFT design verification and MemoryBist Controllers. They should be capable of developing comprehensive verification environments and working with parasitic annotated simulations.
Broadcom offers a competitive compensation package with a base salary range of $119,000 - $190,000, plus potential annual bonuses and equity awards. The benefits package is comprehensive, including medical, dental, and vision insurance, 401(k) with company matching, ESPP, and various paid time off options.
This role presents an excellent opportunity for a seasoned verification engineer to work on cutting-edge technology in data center connectivity. The position combines technical challenges with the stability and resources of a global technology leader, making it an attractive opportunity for professionals looking to advance their careers in mixed-signal design verification.
Requirements For Mixed-Signal Design Verification and Validation Engineer
- BSc in Electrical Engineering or Computer Engineering with 8+ years experience or MSc with 6+ years experience in Mixed Signal Design Verification
- Experience with SV UVM, SV RNM and verification coverage matrix
- Experience writing regression tests, developing checker, writing assertions and developing verification plan
- Knowledge of analog mixed-signal building blocks (ADCs, DACs, PLLs and SerDes)
- Experience with generating randomized vectors for analog and digital behavioral model verification
- Knowledge of standard industry EDA tools - Synopsys/Cadence
- Experience with GLS with & without parasitic annotated simulations
- Experience in verification of DFT design, architecture, and microarchitecture
- Strong written and verbal communication skills
- Self starter and team player
Benefits For Mixed-Signal Design Verification and Validation Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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