Software Engineer, Compiler, Scheduling and Optimization, Silicon

Google is seeking a Software Engineer to join their EdgeTPU compiler team, focusing on core optimization and scheduling algorithms for their next-generation compiler framework. This role is critical in developing and implementing compiler technologies that power Google's AI/ML capabilities on silicon devices.

The position involves working with cutting-edge technology in compiler development, specifically focusing on Multi-Level Intermediate Representation (MLIR)-based compiler frameworks for EdgeTPU. You'll be responsible for designing and implementing optimization algorithms that directly impact the performance of AI/ML workloads on Google devices, including the latest Generative AI models.

This is an excellent opportunity for someone with strong compiler development experience and an interest in hardware/software co-optimization. You'll work closely with EdgeTPU architects to design next-generation architectures and collaborate with product managers and researchers to identify emerging Machine Learning trends and use cases.

The role offers competitive compensation ($141,000-$202,000 base salary plus bonus and equity) and the chance to work at Google's offices in either Mountain View, CA or Bellevue, WA. You'll be part of a team that's pushing the boundaries of AI/ML performance optimization at the hardware level, making a direct impact on Google's next-generation devices and technologies.

The ideal candidate will have at least 2 years of experience with software development, strong knowledge of data structures and algorithms, and specific experience with compiler optimizations and parallelization. Experience with MLIR, LLVM, accelerator-based architectures, and machine learning architectures is highly valued.